Stacked structure with interposer

ABSTRACT

Stacked structures having interposers adhered to packaging substrates are disclosed. In one example, a stacked structure can include a laminate substrate. The stacked structure can also include an interposer mounted on the laminate substrate without solder, for example by an electrically nonconductive adhesive layer. A plurality of conductive vias can be extending through the interposer, and through the nonconductive adhesive layer if present, and connecting to the laminate substrate. The stacked structure can also include a redistribution layer (RDL) adjacent to the interposer. The RDL can be configured to electrically connect to an electronic device. Methods for forming such stacked structures are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application No.63/239,783, filed Sep. 1, 2021, titled “BONDED STRUCTURE WITHINTERPOSER”, the disclosure of which is incorporated herein by referencein its entirety for all purposes.

BACKGROUND Field

The field generally relates to stacked structures, and in particular, tostacked electronic components for packaging or mounting to a board,including interposers and packaging substrates.

Description of the Related Art

Packaging multiple dies into an electronic system may involve assemblingmultiple dies onto a substrate with solder balls, thermal conductivebonding (TCB), etc. As assemblies become finer, it becomes harder toconnect numerous contacts to the substrate. Introducing a redistributionlayer (RDL) between the substrate and the dies having fine lines andspacings can provide better connectivity. However, RDL may have aroughly 1-micron alignment spacing. At the 1-micron scale, thesubstrate, e.g., printed circuit board (PCB), tends to be wavy and nothave a smooth surface, so it is hard to align a RDL to the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Specific implementations will now be described with reference to thefollowing drawings, which are provided by way of example, and notlimitation.

FIG. 1 schematically shows an example stacked structure according tosome embodiments of the disclosed technology.

FIGS. 2A-2E are schematic cross sections illustrating an example processof forming an stacked structure shown in FIG. 1 .

FIGS. 3A-3F are schematic cross sections illustrating another exampleprocess of forming an stacked structure shown in FIG. 1 .

FIGS. 4A-4D are schematic cross sections illustrating yet anotherexample process of forming an stacked structure shown in FIG. 1 .

FIGS. 5A-5D are schematic cross sections showing example stackedstructures with more than one interposer.

FIGS. 6A-6B are schematic cross sections illustrating example uses ofthe disclosed stacked structures in packages systems.

DETAILED DESCRIPTION

Packaging multiple dies into an electronic system may involve firstassembling dies on an interposer and then soldering the dies andinterposer assembly onto a packaging substrate, which in turn can bemounted to a system board. The interposer with a redistribution layer ontop can provide fine lines and spacings. However, the soldering processmay involve raising the temperature then lowering the temperature at theinterface, which creates stresses at the interface. There remains acontinuing need for simplifying packaging processes and improvingelectrical performances of packaged electronic systems.

In some embodiments, the present disclosure provides a way of assemblinginterposers with a packaging substrate without the use of solder. Insome embodiments, the present disclosure provides a stacked structurehaving more than one interposer per substrate, adhered to the packagingsubstrate without solder. The stacked structure may be used inmulti-chip modules having more than one substrate.

FIG. 1 shows a stacked structure 100 having a substrate, e.g., aninterposer, adhered to a packaging substrate. The stacked structure 100can include a laminate substrate 103 (e.g., PCB or ceramic) and aninterposer 101 mounted on the laminate substrate 103 by an electricallynonconductive adhesive layer 102, die attach material (e.g. die attachfilm or paste) or underfill. In some embodiments, the interposersubstrate, or at least the bulk material thereof, has a coefficient ofthermal expansion (CTE) that is below 10 ppm/° C., and more particularlybelow 7 ppm/° C. In some embodiments, the adhesive layer 102 may be acomposite which includes an epoxy that is filled with low coefficient ofthermal expansion (CTE) particles, such as glass beads, to lower theoverall CTE of the composite after hardening. The laminate substrate 103can comprise a plurality of nonconductive layers with embeddedconductive traces 105. The stacked structure 100 can further include aredistribution layer (RDL) 109 on the interposer 101. The RDL 109,having conductors 107 (pads, vias, traces, etc.) embedded in aninsulating material, may be configured to electrically connect to anelectronic device. In some embodiments, the insulating material of theRDL 109 can be a deposited organic material, such as polymers (e.g.,polyamide, polyimide, BCB, etc.). In other embodiments, the insulatingmaterial of the RDL 109 can be a deposited inorganic material such as issuitable for subsequent direct bonding with similar insulating materialsor with semiconductor materials (e.g., silicon oxide, silicon nitride,silicon oxynitride, silicon carbide, silicon carbonitride, etc.). Insome embodiments, the redistribution layer 109 has a line spacing lessthan 5 microns. A plurality of conductive vias 106 can extend throughthe interposer 101 to connect with the conductors 107 of the RDL 109 asshown, and can further extend through the redistribution layer 109 (seeFIGS. 4A-4D and attendant description). In some embodiments, the RDL 109is disposed over the plurality of conductive vias 106. In someembodiments, an additional redistribution layer is further arrangedbetween the interposer 101 and the laminate substrate 103.

The interposer 101 can include a nonconductive material formed of glass,a semiconductor material (e.g., silicon, GaAs, InP, etc.) or ceramic. Insome embodiments, the interposer 101 can comprise a single crystalsemiconductor material. In some embodiments, the interposer 101 has asmaller footprint than that of the laminate substrate 103. In someembodiments, the interposer 101 is devoid of active circuitry (e.g.,transistors). In other embodiments, the interposer 101 can compriseactive circuitry. In some embodiments, the laminate substrate 103 hashigh density interconnections within the substrate, relative to thelaminate substrate 103. In some embodiments, the electricallynonconductive adhesive layer 102 can be formed of a strong adhesivebetween the silicon portion of an interposer 101 and a PCB. In someembodiments, a coefficient of thermal expansion of the nonconductivematerial (e.g., Si) of the interposer 101 substantially matches that ofthe laminate substrate 103 (e.g., PCB).

FIGS. 2A-E illustrate a process of forming a stacked structure shown inFIG. 1 , where like features are referenced by like reference numbersincremented by 100, with suffixes to designate features at differentprocess stages. The process can start with, as shown in FIG. 2A,providing a laminate substrate 203 a and an interposer 201 a. Theinterposer 201 a can have a mounting surface configured to support anelectronic device and a back surface opposite the mounting surface. Theinterposer 201 a can further comprise a plurality of through vias formedin a nonconductive material. The interposer 201 a can further comprisebarrier materials 204 a, and can also include metallization (traces,vias, pads) for local connections or routing other than simple throughvias. The laminate substrate 203 a may comprise metallic traces 205 aand contact pads 2050 a. The process can move to, as shown in FIG. 2B,bonding, adhering or otherwise integrating the back surface of theinterposer 201 b to the laminate substrate 203 b, in the illustratedembodiment by way of a nonconductive adhesive layer 202 b. The processcan move to, as shown in FIG. 2C, removing a portion of the adhesive 202c from the plurality of through vias (e.g., by CO₂ laser ablation) toexpose a plurality of contact pads 2050 c in the laminate substrate 203c. The process can move to, as shown in FIG. 2D, metallizing theplurality of through vias to form a plurality of conductive vias 206 d.The plurality of conductive vias 206 d may be formed such that they arein contact with the contact pads 2050 d of the laminate substrate 203 d.The process can move to, as shown in FIG. 2E, forming a redistributionlayer (RDL) 209 e on the interposer 201 e after bonding the back surfaceof the interposer 201 e to the laminate substrate 203 e. Forming theredistribution layer 209 e may involve growing or depositing theredistribution layer 209 e on the interposer 201 e. As will beappreciated by the skilled artisan, forming RDL involves depositing andpatterning insulating layer(s) and conductive layer(s), such that theredistribution layer 209 e includes conductors 207 e (e.g., vias,traces, pads) embedded in an insulating material and in electricalcommunication with the underlying conductive vias 206 e through theinterposer 201 e.

FIGS. 3A-F illustrates another process of forming a stacked structureshown in FIG. 1 , where like features are referenced by like referencenumbers incremented by 200, with suffixes to designate features atdifferent process stages. The process can start with, as shown in FIG.3A, providing a laminate substrate 303 a and an interposer 301 a. Theinterposer 301 a can have a mounting surface configured to support anelectronic device and a back surface opposite the mounting surface. Theinterposer 301 a can further comprise a plurality of through vias formedin a nonconductive material. The interposer 301 a can further comprisebarrier materials 304 a, and can also include metallization (traces,vias, pads) for local connections or routing other than simple throughvias. The laminate substrate 303 a may comprise metallic traces 305 aand contact pads 3050 a. The process can move to, as shown in FIG. 3B,bonding, adhering or otherwise integrating the back surface of theinterposer 301 b to the laminate substrate 303 b, in the illustratedembodiment by way of a nonconductive adhesive layer 302 b. The processcan move to, as shown in FIG. 3C, removing a portion of the adhesive 302c from the plurality of through vias to expose a plurality of contactpads 3050 c in the laminate substrate 303 c. The process can move to, asshown in FIG. 3D, metallizing the plurality of through vias to form aplurality of conductive vias 306 d. The plurality of conductive vias 306d may be formed such that they are in contact with the contact pads 3050d of the laminate substrate 303 d. The process can move to forming aredistribution layer on the interposer after bonding the back surface ofthe interposer to the laminate substrate. Up to this point, the processof FIGS. 3A-3D can be similar to that described for FIGS. 2A-2D.

In this embodiment, forming the redistribution layer can be achieved byway of a transfer process, as shown in FIG. 3E and FIG. 3F. For example,as shown in FIG. 3E, forming the redistribution layer may involveproviding a preformed RDL 309 e and bonding the preformed RDL 309 e tothe interposer 301 e by an intervening adhesive (not shown). Theredistribution layer 309 e may include conductors 307 e (e.g., traces,vias, pads) embedded in an insulating material. Alternatively, formingthe redistribution layer may involve providing a preformed RDL anddirectly bonding the preformed RDL to the interposer without anintervening adhesive (e.g., by a hybrid direct bonding process). Theperformed RDL 309 e can be formed on a carrier 312 e (such as asemiconductor or glass carrier). As shown in FIG. 3F, the carrier 312 ecan be removed from the RDL 309 f after transferring the RDL 309 f tothe interposer 301 f. Example RDL transfer processes are described inU.S. patent application Ser. No. 17/171,351, the content of which ishereby incorporated by reference herein in its entirety and for allpurposes.

FIGS. 4A-D illustrates yet another process of forming a stackedstructure shown in FIG. 1 , where like features are referenced by likereference numbers incremented by 300, with suffixes to designatefeatures at different process stages. In some examples, the process canstart with, as shown in FIG. 4A, providing a laminate substrate 403 aand an interposer 401 a. The interposer 401 a can have a mountingsurface configured to support an electronic device and a back surfaceopposite the mounting surface. The laminate substrate 403 a may comprisemetallic traces 405 a and contact pads 4050 a. Next, the process canmove to forming a redistribution layer (RDL) 409 a on the mountingsurface of the interposer 401 a. As will be appreciated by the skilledartisan, forming RDL involves depositing and patterning insulatinglayer(s) and conductive layer(s), such that the redistribution layer 409a includes conductors 407 a (e.g., vias, traces, pads) embedded in aninsulating material. In some embodiments, a plurality of through viasextend through both the interposer 401 a and the RDL 409 a, and can belined with barrier materials 404 a as shown. The process can move to, asshown in FIG. 4B, bonding, adhering or otherwise integrating the backsurface of the interposer 401 b to the laminate substrate 403 b, in theillustrated embodiment by way of a nonconductive adhesive layer 402 b.The process can move to, as shown in FIG. 4C, removing a portion of theadhesive 403 c from the plurality of through vias to expose a pluralityof contact pads 4050 c in the laminate substrate 403 c. The process canmove to, as shown in FIG. 4D, metallizing the plurality of through viasto form a plurality of conductive vias 406 d which extend through boththe interposer 401 d and the RDL 409 d, and connect to the conductors407 d of the RDL 409 d to the contact pads 4050 d of the laminatesubstrate 403 d.

Following the processes illustrated in FIGS. 2A-2E, FIGS. 3A-3F, orFIGS. 4A-4D, at least one integrated device die can be attached onto theredistribution layer, by way of solder bonding, adhesive bonding, ordirect bonding without an intervening adhesive. In some examples wherethe integrated device die is attached to the redistribution layer by wayof solder bonding, an underfill may further be provided between theintegrated device die and the redistribution layer. The underfill mayhave the capability to flow in between the die and the redistributionlayer to provide mechanical protection of the solder ball joinings. Insome embodiments, the underfill may be a composite which includes anepoxy that is filled with low coefficient of thermal expansion (CTE)particles, such as glass beads, to lower the overall CTE of thecomposite after hardening.

In some stacked structures as shown in FIG. 5A and FIG. 5B, where likefeatures to those of FIG. 1 are referenced by like reference numbersincremented by 400, with suffixes to designate features at differentprocess stages, more than one interposer is integrated with a laminatesubstrate. The more than one interposer 501 a, 501 b may be integratedwith the substrate 503 a, 503 b by more than one respective adhesivelayer 502 a, 502 b. Alternatively, the more than one interposer may beintegrated with the substrate by a common continuous or patternedadhesive. At least one integrated device die 523 b can be attached tothe same RDL (e.g., 509 a or 509 b). For example, integrated device die523 b may be integrated and electrically connected to the RDL 509 b, inthe illustrated embodiment by solder balls 521 b. As described above,the laminate substrate 503 a, 503 b may comprise metallic traces 505 a,505 b and contact pads 5050 a, 5050 b. The RDL 509 a, 509 b may includeconductors 507 a, 507 b (e.g., traces, vias, pads). The interposer 501a, 501 b may be bonded, adhered or otherwise integrated to the laminatesubstrate 503 a, 503 b, in the illustrated embodiment by adhesive 502 a,502 b. A plurality of conductive vias 506 a, 506 b through theinterposer 501 a, 501 b may be in contact with the contact pads 5050 a,5050 b of the laminate substrate, and may extend through both theinterposer 501 a, 501 b and the RDL 509 a, 509 b as shown in FIGS.4A-5B, or may extend through the interposer and connect with overlyingRDL as shown in FIGS. 1-3F. In some embodiments, one or more RDLs andinterposers mounted to the same substrate can comprise the same orgenerally similar structure. In some embodiments, one or more RDLs andinterposers mounted to the same substrate can comprise differentstructures. In some embodiments, one or more RDLs and interposersmounted to the same substrate can comprise functionally similarstructures. In some embodiments, one or more RDLs and interposersmounted to the same substrate can comprise functionally differentstructures.

FIGS. 5C-5D illustrate stacked structures similar to those of FIGS. 5Aand 5B, and like reference numbers are used to reference like features.The difference is that FIGS. 5C-5D illustrate integrated device dies 523b direct hybrid bonded to the RDL 509 b of or on the interposer 509 b,without intervening solder or other adhesive layers.

As shown in FIG. 6A, the disclosed stacked structures may be used inpackages systems to provide a signal pathway that transfers a signalfrom the laminate substrate 603, through an interposer 601 by some ofthe conductive vias, through the redistribution layer 609, to anintegrated device die 623 (e.g., CPU, GPU, memory stacks, etc.), and inthe opposite direction. The integrated device dies 623 may be solderedto redistribution layers 609 by solder balls 641, and may communicatewith one another through the redistribution layer(s) 609. FIG. 6A alsoshows another integrated device die 624 that is directly connected tothe laminate substrate 603 by way of additional solder balls 631. Thelaminate substrate 603 may be soldered to a system board 625 by solderballs 621. This integrated device die 624 is shown communicating withthe other device dies 623 by way of the RDL 609, interposer 601 andlaminate substrate 603. The disclosed stacked structures thus may alsoprovide a signal pathway that transfers a signal from an integrateddevice die, through the redistribution layer, to another integrateddevice die, connected to the redistribution layer(s) or to the laminatesubstrate, and in the other direction. The interposer 601 iselectrically and mechanically connected to the laminate substrate 603without solder.

FIG. 6B is similar to FIG. 6A, except that the integrated device dies623 are shown direct hybrid bonded to the RDL 609 on the interposer 601.

Redistribution Layer

Integrated device packages can use a redistribution layer (RDL) toredistribute signals from one or more integrated device dies in thepackage to other devices (e.g., other devices outside the footprint ofthe integrated device die). The RDL can include traces that extendlaterally, for connecting pads on top that are laterally offset withrespect to pads on the bottom. Such lateral extension can connectfeatures on the bottom and top of the RDL that have different pitches(fan-out or fan-in), simply laterally offset and/or can electricallyconnect multiple dies. The RDL may comprise conductors embedded in aninsulating or nonconductive material. An electronic component (e.g., anintegrated device die) can be connected to a redistribution layer, whichcan comprise conductive routing traces to route signals laterallyoutside the footprint of the electronic component. In some embodiments,the RDL comprises metallic traces or conductors extending laterally inorder to transfer signals inwardly (fan-in) or outwardly (fan-out) fromintegrated device dies mounted to the RDL. In some embodiments, theinterconnect structure may comprise one or a few layers. Beneficially,the RDL can include numerous or dense interconnects and signal linesthat can convey a significant number of signals between the dies.

In some embodiments, fan-out redistribution can convey signals fromfinely-pitched bond pads of an integrated device die to other deviceslaterally spaced from the die. In some implementations, fan-out RDL canconvey signals from dense contacts of a die to more spread out leads orcontact pads configured to connect to a system board (e.g., a printedcircuit board, or PCB). In some implementations, \ fan-out RDL canconvey signals from the die to other devices, such as other integrateddevice dies, etc. In some packages that include multiple integrateddevice dies, the dies may be mounted to a sacrificial carrier, and amolding compound can be provided over the dies and carrier. Thesacrificial carrier can be removed, and the molded device dies can beflipped over. The RDL can be deposited over the molding compound and thedevice dies to form a reconstituted wafer. The reconstituted wafer canbe singulated into a plurality of packages, with each package includingone or multiple dies connected to an RDL.

Integrated Device Dies

In some embodiments, one or more of the plurality of integrated devicedies can be flip-chip mounted to the RDL. The plurality of integrateddevice dies can comprise any suitable type of device die. For example,one or more of the plurality of integrated device dies can comprise anelectronic component such as a processor die, a memory die, amicroelectromechanical systems (MEMS) die, an optical device, or anyother suitable type of device die. In other embodiments, the electroniccomponent can comprise a passive device such as a capacitor, inductor,or other surface-mounted device. Circuitry (such as active componentslike transistors) can be patterned at or near active surface(s) of oneor more of the plurality of integrated device dies in variousembodiments. The active surfaces may be on a side of one or more of theplurality of integrated device dies which is opposite respectivebacksides of the one or more of the plurality of integrated device dies.The backsides may or may not include any active circuitry or passivedevices. In various embodiment, the integrated device dies mounted to asubstrate may be the same type of integrated device die or a differenttype of device die.

An integrated device die can comprise a bonding surface and a backsurface opposite the bonding surface. The bonding surface can have aplurality of conductive bond pads including a conductive bond pad, and anon-conductive material proximate to the conductive bond pad. In someembodiments, the conductive bond pads of the integrated device die canbe directly bonded to the corresponding conductive pads of the RDLwithout an intervening adhesive, and the non-conductive material of theintegrated device die can be directly bonded to a portion of thecorresponding non-conductive material of the RDL without an interveningadhesive. Directly bonding without an adhesive is described furtherbelow, and in U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070;8,163,373; 8,389,378; 7,485,968; 8,735,219; 9,385,024; 9,391,143;9,431,368; 9,953,941; 9,716,033; 9,852,988; 10,032,068; 10,204,893;10,434,749; and 10,446,532, the contents of each of which are herebyincorporated by reference herein in their entirety and for all purposes.In some embodiments, the plurality of integrated device dies canalternatively be bonded to the RDL by way of a thermal conductivebonding (TCB).

Examples of Direct Bonding Methods and Directly Bonded Structures

Various embodiments disclosed herein relate to directly bondedstructures in which two elements can be directly bonded to one anotherwithout an intervening adhesive. Two or more elements (such asintegrated device dies, wafers, interposers, redistribution layers,etc.) may be stacked on or bonded to one another to form a bondedstructure. Conductive contact pads of one element may be electricallyconnected to corresponding conductive contact pads of another element.Any suitable number of elements can be stacked in the bonded structure.The contact pads may comprise metallic pads formed in a nonconductivebonding region, and may be connected to underlying metallization, suchas a redistribution layer (RDL).

In some embodiments, the elements are directly bonded to one anotherwithout an adhesive. In various embodiments, a non-conductive ordielectric material of a first element can be directly bonded to acorresponding non-conductive or dielectric field region of a secondelement without an adhesive. The non-conductive material can be referredto as a nonconductive bonding region or bonding layer of the firstelement. In some embodiments, the non-conductive material of the firstelement can be directly bonded to the corresponding non-conductivematerial of the second element using dielectric-to-dielectric bondingtechniques. For example, dielectric-to-dielectric bonds may be formedwithout an adhesive using the direct bonding techniques disclosed atleast in U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entirecontents of each of which are incorporated by reference herein in theirentirety and for all purposes.

In various embodiments, hybrid direct bonds can be formed without anintervening adhesive. For example, dielectric bonding surfaces can bepolished to a high degree of smoothness. The bonding surfaces can becleaned and exposed to a plasma and/or etchants to activate thesurfaces. In some embodiments, the surfaces can be terminated with aspecies after activation or during activation (e.g., during the plasmaand/or etch processes). Without being limited by theory, in someembodiments, the activation process can be performed to break chemicalbonds at the bonding surface, and the termination process can provideadditional chemical species at the bonding surface that improves thebonding energy during direct bonding. In some embodiments, theactivation and termination are provided in the same step, e.g., a plasmaor wet etchant to activate and terminate the surfaces. In otherembodiments, the bonding surface can be terminated in a separatetreatment to provide the additional species for direct bonding. Invarious embodiments, the terminating species can comprise nitrogen.Further, in some embodiments, the bonding surfaces can be exposed tofluorine. For example, there may be one or multiple fluorine peaks nearlayer and/or bonding interfaces. Thus, in the directly bondedstructures, the bonding interface between two dielectric materials cancomprise a very smooth interface with higher nitrogen content and/orfluorine peaks at the bonding interface. Additional examples ofactivation and/or termination treatments may be found throughout U.S.Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents ofeach of which are incorporated by reference herein in their entirety andfor all purposes.

In various embodiments, conductive contact pads of the first element canalso be directly bonded to corresponding conductive contact pads of thesecond element. For example, a hybrid bonding technique can be used toprovide conductor-to-conductor direct bonds along a bond interface thatincludes covalently direct bonded dielectric-to-dielectric surfaces,prepared as described above. In various embodiments, theconductor-to-conductor (e.g., contact pad to contact pad) direct bondsand the dielectric-to-dielectric hybrid bonds can be formed using thedirect bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033and 9,852,988, the entire contents of each of which are incorporated byreference herein in their entirety and for all purposes.

For example, dielectric bonding surfaces can be prepared and directlybonded to one another without an intervening adhesive as explainedabove. Conductive contact pads (which may be surrounded by nonconductivedielectric field regions) may also directly bond to one another withoutan intervening adhesive. In some embodiments, the respective contactpads can be recessed below exterior (e.g., upper) surfaces of thedielectric field or nonconductive bonding regions, for example, recessedby less than 30 nm, less than 20 nm, less than 15 nm, or less than 10nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of4 nm to 10 nm. The nonconductive bonding regions can be directly bondedto one another without an adhesive at room temperature in someembodiments and, subsequently, the bonded structure can be annealed.Upon annealing, the contact pads can expand and contact one another toform a metal-to-metal direct bond. Beneficially, the use of hybridbonding techniques, such as Direct Bond Interconnect, or DBI®, availablecommercially from Xperi of San Jose, Calif., can enable high density ofpads connected across the direct bond interface (e.g., small or finepitches for regular arrays). In some embodiments, the pitch of thebonding pads, or conductive traces embedded in the bonding surface ofone of the bonded elements, may be less 40 microns or less than 10microns or even less than 2 microns. For some applications the ratio ofthe pitch of the bonding pads to one of the dimensions of the bondingpad is less than 5, or less than 3 and sometimes desirably less than 2.In other applications the width of the conductive traces embedded in thebonding surface of one of the bonded elements may range between 0.3 to 3microns. In various embodiments, the contact pads and/or traces cancomprise copper, although other metals may be suitable.

Thus, in direct bonding processes, a first element can be directlybonded to a second element without an intervening adhesive. In somearrangements, the first element can comprise a singulated element, suchas a singulated integrated device die. In other arrangements, the firstelement can comprise a carrier or substrate (e.g., a wafer) thatincludes a plurality (e.g., tens, hundreds, or more) of device regionsthat, when singulated, form a plurality of integrated device dies.Similarly, the second element can comprise a singulated element, such asa singulated integrated device die. In other arrangements, the secondelement can comprise a carrier or substrate (e.g., a wafer).

As explained herein, the first and second elements can be directlybonded to one another without an adhesive, which is different from adeposition process. In one application, a width of the first element inthe bonded structure can be similar to a width of the second element. Insome other embodiments, a width of the first element in the bondedstructure can be different from a width of the second element. The widthor area of the larger element in the bonded structure may be at least10% larger than the width or area of the smaller element. The first andsecond elements can accordingly comprise non-deposited elements.Further, directly bonded structures, unlike deposited layers, caninclude a defect region along the bond interface in which nanovoids arepresent. The nanovoids may be formed due to activation of the bondingsurfaces (e.g., exposure to a plasma). As explained above, the bondinterface can include concentration of materials from the activationand/or last chemical treatment processes. For example, in embodimentsthat utilize a nitrogen plasma for activation, a nitrogen peak can beformed at the bond interface. In embodiments that utilize an oxygenplasma for activation, an oxygen peak can be formed at the bondinterface. In some embodiments, the bond interface can comprise siliconoxynitride, silicon oxycarbonitride, or silicon carbonitride. Asexplained herein, the direct bond can comprise a covalent bond, which isstronger than van Der Waals bonds. The bonding layers can also comprisepolished surfaces that are planarized to a high degree of smoothness.

In various embodiments, the metal-to-metal bonds between the contactpads can be joined such that copper grains grow into each other acrossthe bond interface. In some embodiments, the copper can have grainsoriented along the 111 crystal plane for improved copper diffusionacross the bond interface. The bond interface can extend substantiallyentirely to at least a portion of the bonded contact pads, such thatthere is substantially no gap between the nonconductive bonding regionsat or near the bonded contact pads. In some embodiments, a barrier layermay be provided under the contact pads (e.g., which may include copper).In other embodiments, however, there may be no barrier layer under thecontact pads, for example, as described in US 2019/0096741, which isincorporated by reference herein in its entirety and for all purposes.

In one aspect, a stacked structure is disclosed. The stacked structurecan include a laminate substrate. The stacked structure can also includean interposer mounted on the laminate substrate by an adhesive layer. Aplurality of conductive vias are extending through the interposer andthe nonconductive adhesive layer and connecting to the laminatesubstrate. The stacked structure can also include a redistribution layer(RDL) adjacent to the interposer.

In one embodiment, the RDL is on the interposer.

In one embodiment, the RDL is between the interposer and the adhesivelayer.

In one embodiment, the stacked structure further includes an additionalRDL between the interposer and the adhesive layer.

In one embodiment, the RDL is configured to electrically connect to anelectronic device.

In one embodiment, the plurality of conductive vias extend through theredistribution layer.

In one embodiment, the interposer comprises a nonconductive materialformed of glass, semiconductor and/or ceramic.

In one embodiment, the redistribution layer comprises conductorsembedded in an insulating material.

In one embodiment, the redistribution layer is grown or deposited on theinterposer.

In one embodiment, the redistribution layer is integrated with theinterposer by an intervening adhesive.

In one embodiment, the redistribution layer is directly bonded to theinterposer without an intervening adhesive.

In one embodiment, the stacked structure further includes at least oneintegrated device die arranged on the redistribution layer.

In one embodiment, the at least one integrated device die iselectrically connected to the redistribution layer.

In one embodiment, the at least one integrated device die is integratedwith the redistribution layer by soldering.

In one embodiment, the at least one integrated device die is integratedwith the redistribution layer by an intervening adhesive.

In one embodiment, the at least one integrated device die is directlybonded to the redistribution layer without an intervening adhesive.

In one embodiment, the laminate substrate comprises a printed circuitboard and/or wherein the laminate substrate comprises ceramic.

In one embodiment, the adhesive layer comprises an electricallynonconductive adhesive and/or an underfill.

In one embodiment, the stacked structure can also include a signalpathway configured to transfer a signal from the laminate substrate,through the interposer by way of the plurality of conductive vias,through the redistribution layer, to one of the at least one integrateddevice die, and vice versa.

In one embodiment, the stacked structure can also include a signalpathway configured to transfer a signal from one of the at least oneintegrated device die, through the redistribution layer, to another oneof the at least one integrated device die, and vice versa.

In one embodiment, the stacked structure can also include an additionalredistribution layer arranged between the interposer and the laminatesubstrate.

In one embodiment, the interposer is devoid of active circuitry.

In one embodiment, the RDL is disposed over the plurality of conductivevias.

In one embodiment, the plurality of conductive vias extend through fromthe interposer to the RDL.

In one aspect, a stacked structure is disclosed. The stacked structurecan include a laminate substrate. The stacked structure can also includeat least two interposers arranged on the laminate substrate. Each of theat least two interposers are integrated with the laminate substrate byone or more nonconductive adhesive layers.

In one embodiment, each of the at least two interposers comprises arespective plurality of conductive vias formed in a nonconductivematerial.

In one embodiment, the stacked structure can also include a respectiveredistribution layer arranged on each of the at least two interposers.

In one embodiment, the stacked structure can also include a respectiveredistribution layer arranged on each of the at least two interposers.The respective plurality of conductive vias extends through therespective redistribution layer.

In one embodiment, the nonconductive material is formed of glass,semiconductor and/or ceramic.

In one embodiment, the respective redistribution layer comprisesconductors embedded in an insulating material.

In one embodiment, the respective redistribution layer is grown ordeposited on the interposer.

In one embodiment, the respective redistribution layer is integratedwith the interposer by an intervening adhesive.

In one embodiment, the respective redistribution layer is directlybonded to the interposer without an intervening adhesive.

In one embodiment, the stacked structure can also include at least oneintegrated device die arranged on the respective redistribution layer.

In one embodiment, the at least one integrated device die is integratedwith the respective redistribution layer by soldering.

In one embodiment, the at least one integrated device die is integratedwith the respective redistribution layer by an intervening adhesive.

In one embodiment, the at least one integrated device die is directlybonded to the respective redistribution layer without an interveningadhesive.

In one embodiment, the laminate substrate is a printed circuit boardand/or wherein the laminate substrate comprises ceramic.

In one embodiment, the respective adhesive layer comprises anelectrically nonconductive adhesive and/or an underfill.

In one embodiment, the stacked structure can also include a signalpathway configured to transfer a signal from the laminate substrate,through one of the at least two interposers by way of the respectiveplurality of conductive vias, through the respective redistributionlayer, to one of the at least one integrated device die, and vice versa.

In one embodiment, the stacked structure can also include an additionalredistribution layer arranged between one of the at least twointerposers and the laminate substrate.

In one aspect, a method of forming a stacked structure is disclosed. Themethod can include providing a laminate substrate. The method can alsoinclude providing an interposer. The interposer is having a mountingsurface configured to support an electronic device and a back surfaceopposite the mounting surface. The method can include integrating theinterposer with the laminate substrate without solder. A plurality ofconductive vias extend through the interposer to connect to the laminatesubstrate.

In one embodiment, the interposer comprises a plurality of through viasformed in a nonconductive material.

In one embodiment, the method can also include forming a redistributionlayer on the interposer after bonding the back surface of the interposerto the laminate substrate.

In one embodiment, the method can also include forming a redistributionlayer on the interposer before bonding the back surface of theinterposer to the laminate substrate.

In one embodiment, the plurality of through vias extends through theredistribution layer.

In one embodiment, the nonconductive material is formed of glass,semiconductor and/or ceramic.

In one embodiment, integrating the interposer with the laminatesubstrate includes providing a nonconductive adhesive, and the methodincludes removing a portion of the adhesive from the plurality ofthrough vias to expose a plurality of contact pads in the laminatesubstrate. The method can also include metallizing the plurality ofthrough vias to form a plurality of conductive vias.

In one embodiment, the redistribution layer comprises conductorsembedded in an insulating material.

In one embodiment, forming the redistribution layer comprises growing ordepositing the redistribution layer on the interposer.

In one embodiment, forming the redistribution layer comprises bondingthe redistribution layer to the interposer by an intervening adhesive,where the redistribution layer has been preformed.

In one embodiment, forming the redistribution layer comprises directlybonding the redistribution layer to the interposer without anintervening adhesive, where the redistribution layer has been preformed.

In one embodiment, the method can also include attaching at least oneintegrated device die onto the redistribution layer.

In one embodiment, attaching the at least one integrated device diecomprises solder bonding the at least one integrated device die to theredistribution layer.

In one embodiment, attaching the at least one integrated device diecomprises adhesive bonding the at least one integrated device die to theredistribution layer.

In one embodiment, attaching the at least one integrated device diecomprises direct bonding the at least one integrated device die to theredistribution layer without an intervening adhesive.

In one embodiment, the laminate substrate comprises a printed circuitboard and/or wherein the laminate substrate comprises ceramic.

In one embodiment, integrating the interposer with the laminatesubstrate includes providing an underfill.

In one embodiment, the method can also include providing an additionalredistribution layer between the interposer and the laminate substrate.

In one embodiment, integrating the interposer with the laminatesubstrate includes providing a nonconductive adhesive, and the methodalso includes removing a portion of the adhesive from the plurality ofthrough vias and metallizing the plurality of through vias aresubsequent to bonding the back surface of the interposer to the laminatesubstrate.

In one embodiment, the interposer has a smaller footprint than that ofthe laminate substrate.

In one embodiment, each of the at least two interposers has a smallerfootprint than that of the laminate substrate.

In one embodiment, a coefficient of thermal expansion of thenonconductive material substantially matches that of the laminatesubstrate.

In one embodiment, the redistribution layer has a line spacing less than5 microns.

In one embodiment, each of the at least two redistribution layers has aline spacing less than 5 microns.

In one aspect, a stacked structure is disclosed. The stacked structurecan include a laminate substrate. The stacked structure can also includea substrate mounted on the laminate substrate without solder. Aplurality of conductive vias extend through the substrate and connect tothe laminate substrate. The stacked structure can also include aredistribution layer (RDL) adjacent to the substrate.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,”“include,” “including” and the like are to be construed in an inclusivesense, as opposed to an exclusive or exhaustive sense; that is to say,in the sense of “including, but not limited to.” The word “coupled”, asgenerally used herein, refers to two or more elements that may be eitherdirectly connected, or connected by way of one or more intermediateelements. Likewise, the word “connected”, as generally used herein,refers to two or more elements that may be either directly connected, orconnected by way of one or more intermediate elements. Additionally, thewords “herein,” “above,” “below,” and words of similar import, when usedin this application, shall refer to this application as a whole and notto any particular portions of this application. Moreover, as usedherein, when a first element is described as being “on” or “over” asecond element, the first element may be directly on or over the secondelement, such that the first and second elements directly contact, orthe first element may be indirectly on or over the second element suchthat one or more elements intervene between the first and secondelements. Where the context permits, words in the above DetailedDescription using the singular or plural number may also include theplural or singular number respectively. The word “or” in reference to alist of two or more items, that word covers all of the followinginterpretations of the word: any of the items in the list, all of theitems in the list, and any combination of the items in the list.

Moreover, conditional language used herein, such as, among others,“can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and thelike, unless specifically stated otherwise, or otherwise understoodwithin the context as used, is generally intended to convey that certainembodiments include, while other embodiments do not include, certainfeatures, elements and/or states. Thus, such conditional language is notgenerally intended to imply that features, elements and/or states are inany way required for one or more embodiments.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the disclosure. Indeed, the novel apparatus, methods, andsystems described herein may be embodied in a variety of other forms;furthermore, various omissions, substitutions and changes in the form ofthe methods and systems described herein may be made without departingfrom the spirit of the disclosure. For example, while blocks arepresented in a given arrangement, alternative embodiments may performsimilar functionalities with different components and/or circuittopologies, and some blocks may be deleted, moved, added, subdivided,combined, and/or modified. Each of these blocks may be implemented in avariety of different ways. Any suitable combination of the elements andacts of the various embodiments described above can be combined toprovide further embodiments. The accompanying claims and theirequivalents are intended to cover such forms or modifications as wouldfall within the scope and spirit of the disclosure.

What is claimed is:
 1. A stacked structure, comprising: a laminatesubstrate; an interposer mounted on the laminate substrate by anadhesive layer, a plurality of conductive vias extending through theinterposer and the nonconductive adhesive layer and connecting to thelaminate substrate; and a redistribution layer (RDL) adjacent to theinterposer.
 2. The stacked structure of claim 1, wherein the RDL is onthe interposer.
 3. The stacked structure of claim 1, wherein the RDL isbetween the interposer and the adhesive layer.
 4. The stacked structureof claim 2, further comprising an additional RDL between the interposerand the nonconductive adhesive layer.
 5. The stacked structure of claim1, wherein the plurality of conductive vias extend through theredistribution layer.
 6. The stacked structure of claim 1, wherein theinterposer comprises a nonconductive material formed of glass,semiconductor and/or ceramic.
 7. The stacked structure of claim 1,wherein the redistribution layer is integrated with the interposer by anintervening adhesive.
 8. The stacked structure of any one of claim 1,wherein the redistribution layer is directly bonded to the interposerwithout an intervening adhesive.
 9. A stacked structure comprising: alaminate substrate; and at least two interposers arranged on thelaminate substrate, wherein each of the at least two interposers areintegrated with the laminate substrate by one or more nonconductiveadhesive layers.
 10. The stacked structure of claim 9, wherein each ofthe at least two interposers comprises a respective plurality of throughinterposer conductive vias formed in a nonconductive material.
 11. Amethod of forming a stacked structure, the method comprising: providinga laminate substrate; providing an interposer, the interposer having amounting surface configured to support an electronic device and a backsurface opposite the mounting surface; and integrating the interposerwith the laminate substrate without solder, wherein a plurality ofconductive vias extend through the interposer to connect to the laminatesubstrate.
 12. The method of claim 11, wherein the interposer isintegrated with the laminate substrate by way of an adhesive layer,wherein the plurality of conductive vias extend through the adhesivelayer.
 13. The method of claim 11, further comprising forming aredistribution layer on the interposer after integrating the interposerwith the laminate substrate.
 14. The method of claim 11, furthercomprising forming a redistribution layer on the interposer beforeintegrating the interposer with the laminate substrate.
 15. The methodof claim 12, further comprising: removing a portion of the adhesivelayer to expose a plurality of contact pads in the laminate substrate;and metallizing a plurality of through vias in the interposer alignedwith the plurality of contact pads to form the plurality of conductivevias.
 16. The method of claims 13, wherein forming the redistributionlayer comprises bonding the redistribution layer to the interposer by anintervening adhesive, wherein the redistribution layer has beenpreformed.
 17. The method of claims 13, wherein forming theredistribution layer comprises directly bonding the redistribution layerto the interposer without an intervening adhesive, wherein theredistribution layer has been preformed.
 18. A stacked structure,comprising: a laminate substrate; and a substrate mounted on thelaminate substrate without solder, a plurality of conductive viasextending through the substrate and connecting to the laminatesubstrate; and a redistribution layer (RDL) on a side of the substrateopposite the laminate substrate.